Skip to article frontmatterSkip to article content
Site not loading correctly?

This may be due to an incorrect BASE_URL configuration. See the MyST Documentation for reference.

1Learning Outcomes

🎥 Lecture Video

Recall from earlier that an ISA specifies assembly instructions, machine instructions, and fundamental architecture features like registers, memory access, and instruction execution.

To fully utilize the ISA, we must write machine instructions, which are the bit representations of assembly instructions.

2Instruction Formats

Recall from our discussion of instruction execution and the program counter that all RV32I instructions are word sized.[2] Simplification works for RISC-V: Instructions are same size as a data word (32 bits) so that they can leverage the same hardware for memory access.

How do we go about translating add x1 x2 x3 to the 32-bit word 00000000101010011000100100110011?

RISC-V defines six basic instruction formats, where similar instructions use the same format. Each instruction format divides an instruction word into fields; each field tells the processor something about the instructor.

We hope you treat these two chapters like a puzzle hunt, where you learn how to decipher the rightmost columns of the RISC-V green card and the Instruction Types table.

Footnotes

  1. That being said, many instruction sets are backwards-compatible and evolve over time. e.g., latest PCs with x86 ISA today can still run programs from Intel 8088 (1981)!

    ↩

  2. We cover RV32I (32-bit integer instructions). The same 32-bit instructions are used for RV32, RV64, RV128.

    ↩
L12 RISC-V Procedures
Summary
L13 RISC-V Instruction Formats I
R-Type