I-Type

1Learning Outcomes¶

• Translate between I-type assembly instructions and machine instructions.

• Reason about why load and jalr are I-Type instructions.

• Translate jr and ret pseudoinstructions to machine instructions.

We now turn to our next instruction format: I-Type. While the “I” is for Immediate, the I-Type instruction format is used for a variety of instructions:

• Register-immediate arithmetic instructions

• Load instructions

• The jalr instruction

• (out of scope) Environment calls and breakpoints

The I-Type instruction format is the second and third rows of the instruction format table.

2I-Type: Fields¶

We first discuss arithmetic instructions of the form opname rd rs1 imm like addi, xori, etc. The format is shown in Figure 1:

I-Type Fields:

• Register operands: Notice that the register fields rs1 and rd are in the same positions in I-Type and R-type; this intentional design reduces hardware complexity.

• Constant operand: The immediate field^[1] imm specifies a 12-bit-wide numeric constant. The I-Type has no second source register rs2, so imm reuses those bit positions to encode a larger numeric constant across bits 15 to 31.

  The 12-bit immediate is a two’s complement integer with range $-2^{11} = -2048$ to $2^{11} - 1 = 2047$. Before using this 12-bit-wide value in an operation, the hardware sign-extends it to a 32-bit-wide value.

• Operation fields: opcode, funct3

3Assembly Instruction $\rightarrow$ Machine Instruction¶

Consider Figure 2, which translates addi x15 x1 -50 to a machine instruction.

We follow the steps for translating assembly into machine code from earlier:

1. Determine instruction format type. addi is I-type because it performs arithmetic betwen a register operand and a constant operand. We use the arithmetic instructions table on the RISC-V green card.

2. Determine operation field codes.

   • opcode: 0010011 for all register-immediate arithmetic instructions

   • funct3: 000 for add

3. Translate registers, immediates, etc.

   • rs1: Register x1. Translate 1 to 5-bit unsigned integer representation 00001.

   • rd: Register x15. Translate 15 to 5-bit unsigned integer representation 01111.

   • imm: -50 as 12-bit two’s complement:

     • +50 is 0000 0011 0010.

     • Flip bits: 1111 1100 1101.

     • Add one to get -50: 1111 1100 1110.

4. (if needed) Convert to hexadecimal.

   • We leave this as an exercise to you!

4I-Type vs. R-Type¶

Figure 3 compares the two instruction formats we have seen so far:

Again, good design demands good compromises. If we only had the single R-Type format and specified imm as a 5-bit field replacing rs2, then we’d only be able to represent 32 immediate values. The I-Type field therefore expands the imm field across the R-type’s rs2 and funct7 fields to at least guarantee we can represent a wider range of 2¹² immediate values.

The I-type design’s consistency with R-type simplifies how hardware processes these two instruction formats. Constants are frequently short and can fit into the 12-bit imm field. For larger constants, we must use additional instructions like lui (load upper-immediate), which we discuss later.

Notice the 3-bit funct3 field is not sufficient to specify the 9 register-immediate arithmetic instructions, much less any load instructions. The I-Type therefore still has a few details. Onward!

5Arithmetic Shifts (“I*-Type”)¶

While there is no official “I*-Type” instructions, the RV32I Unprivileged Manual says:

Shifts by a constant are encoded as a specialization of the I-type format.

In this course we will call these “I*-Type” (where the asterisk is “mostly I-Type, save some details”). Consider Table 1 and the following excerpt from the manual:

The operand to be shifted is in rs1, and the shift amount is encoded in the lower 5 bits of the I-immediate field. The right shift type is encoded in bit 30.

Observations:

• Arithmetic bitshift operations need only a 5-bit unsigned immediate, in imm[4:0]. The maximum bitshift is 32; anything larger will shift all data off the register, which is 32 bits wide.

• The upper seven bits^[2] are not part of the immediate and used very similarly to the funct7 field for R-Type instructions sll, srl, and sra.

  • Like with R-type, Bit 30 is a flag that indicates when it is necessary to sign-extend.

  • If Bit 30 is on, insert leading 1’s (for srai).

  • If Bit 30 is off, just zero-extend for srli (and slli, where left-shifts are only ever logical).

6Load Instructions¶

Remember, instruction formats are simply just formats. The operation specifies what the hardware actually does. However, keeping the same instruction format allows us to simplify and reuse certain hardware.

Load instructions are one such example. Recall from an earlier section:

The load word instruction:

• Computes a memory address R[rs1]+imm

• Load a word from this address in memory, M[R[rs1] + imm][31:0] into a destination register, rd.

Loads can therefore use the I-Type instruction format (Figure 4):

• imm, rs1, rd fields

• opcode (as all instructions do). Loads use opcode 000 0011.

• funct3 specifies partial loads and signed/unsigned loads.

Observations:

• The fact that loads perform a memory access is irrelevant to how we specify the instruction. The instruction bits simply provide enough information for the hardware to decode and execute the correct instruction.

• Loads do share some similarities with other I-Type instructions. Notably, loads also perform register-immediate addition to compute the memory address as R[rs1] + imm. Loads can therefore reuse any hardware needed for register-immediate arithmetic instructions.

We recommend reviewing the earier chapter for the description of each load instruction in Table 2.

6.1Load Example¶

Show Explanation

We follow the steps for translating assembly into machine code from earlier:

1. Determine instruction format type. lw is I-type. We use the memory table on the RISC-V green card.

2. Determine operation field codes.

   • opcode: 0000011 for load instructions

   • funct3: 010 for load word

3. Translate registers, immediates, etc.

   • rs1: Base Register x2. Translate 1 to 5-bit unsigned integer representation 00010.

   • rd: Register x14. Translate 14 to 5-bit unsigned integer representation 01110.

   • imm: address offset +8 as 12-bit two’s complement: 0000 0000 1000.

7jalr: I-Type¶

We recommend reviewing jump instructions before continuing:

Jump and Link Register (jalr rd rs1 imm). Link the “return address” (PC + 4) to a register rd. Then perform an unconditional jump by setting PC to R[rs1] + imm.

The jalr instruction can also be supported with the I-Type format (Figure 6):

• imm, rs1, rd fields

• opcode (as all instructions do). jalr uses opcode 110 0111.

• funct3 is not particularly needed, since there is only one jalr instruction. However, because the I-Type format requires it, jalr uses 000.

Observations:

• Like with loads, the fact that jalr accesses PC is irrelevant to how we specify the instruction.

• Like with loads, jalr also performs register-immediate addition, jalr can therefore reuse register-immediate arithmetic hardware to compute the jump address R[rs1] + imm.

8Design Decisions for I-Type¶

This section is intended for you to develop your intuition for I-Type instructions using what you learned in this section.

Consider the I-Type instructions^[3] shown in Table 3, which is a reformatting of the rightmost columns of relevant tables on the RISC-V green card.

See explanation [above].

First question: see explanation [above]. Second question: See a later section.