R-type Instruction Format

1Learning Outcomes¶

• Identify an instruction format type by the opcode field.

• Translate between R-type assembly instructions and machine instructions.

Like with IEEE 754 floating point numbers, the 32 bits of a machine instruction are split into fields. Like floating point, each field has a name and occupies a given set of bit positions (and therefore has a fixed width). Unlike floating point, the field names and locations themselves depend on the instruction type.

As an example, an R-type instruction is shown in Figure 1. The field named opcode occupies the least-significant bits (bit positions 0 to 6); the opcode field is 7 bits wide. Also notice that the assembly instruction opname rd rs1 rs2 shares some nomenclature with instruction fields, but not all. For example, rs1, rs2, and rd are field names, but opname is not.

2R-Type: Fields¶

The R-Type instruction format is the first row of the instruction format table of the RISC-V green card. All register-register arithmetic instructions use R-Type (the “R” is for Register). We now use “arithmetic” to encompass arithmetic and bitwise operations: add, xor, sll, etc. We recommend you reference the arithmetic instructions table as you explore the R-Type instruction format below.

Figure 2 (Figure 1 with less annotation) shows the R-Type format. Notice that all register-register arithmetic instructions have follow the same assembly instruction syntax opname rd rs1 rs2.

Register operands: The three R-Type fields named rs1, rs2, rd map to their equivalent assembly instruction operands. Each field is a 5-bit unsigned integer (0 to 31) corresponding to a register number (x0-x31). Register names (e.g., a0) are translated first into their register number (e.g., x10), then their bit pattern (e.g., 01010).

• rs1: “Source” Register, first operand

• rs2: “Source” Register, second operand

• rd: “Destination” Register gets the result of the arithmetic computation.

Other fields: The assembly instruction operation opname is mapped across three fields: `

• opcode: All R-type instructions have the same 7-bit opcode: 0110011.

• funct3, funct7: The arithmetic operation to perform. funct3 field is 3 bits wide; funct7 is 7 bits wide.

3Assembly Instruction $\rightarrow$ Machine Instruction¶

Consider Figure 3, which translates add x18 x19 x10 to a machine instruction.

1. Determine instruction format type. add is R-type because it performs arithmetic on two register operands. We use the arithmetic instructions table on the RISC-V green card.

2. Determine operation field codes.

   • opcode: 0110011 (for all R-Type instructions).

   • funct3: 000 for add

   • funct7: 0000000 for add

3. Translate registers, immediates, etc.

   • rs1: Register x19. Translate 19 to 5-bit unsigned integer representation 10011.

   • rs2: Register x10. Translate 10 to 5-bit unsigned integer representation 01010.

   • rd: Register x18. Translate 18 to 5-bit unsigned integer representation 10010.

4. (if needed) Convert to hexadecimal.

   • We leave this as an exercise to you!

4Machine Instruction $\rightarrow$ Assembly Instruction¶

Steps for translating machine code into assembly:

1. If needed, convert to binary. Then, find the opcode and use that to determine the instruction format type.

2. Split into fields according to instruction format type.

3. For R-Type, determine the assembly instruction opname with the funct3, funct7 fields.

4. For R-Type, determine register operands and (if needed) register names.

The last two steps are R-Type-specific. In general, you should always do the first two steps, regardless of instruction format type. Then, perform type-specific conversions to reconstruct the original assembly instruction.

Explanation:

1. We have already converted 0x01B342B3 to binary: 0b0000 0001 1011 0011 0100 0010 1011 0011.

   Then, find the opcode and use that to determine the instruction format type. The opcode field is always the lowest 7 bits of the instruction, regardless of format. 0110011 is the opcode for R-Type instructions.

2. Split into fields according to instruction format type.. For translation, it is not particularly useful to visually space out nybbles, as above. In Figure 4, the 32-bit pattern above is visually split into the six fields of the R-Type instruction format.

3. Determine the assembly instruction opname. The funct3 field is 100; the funct7 field is 0000000. We look up these fields on our green card and discover the instruction is xor.

4. Determine registers. Use the register convention table for register names.

   • rd: 10010 is 5, so register x5, aka t0.

   • rs1: 00110 is 6, so register x6, aka t1

   • rs2: 11011 is 27, so register x27, aka s11.

Given the above, the instruction is E. xor t0 t1 s11.

5Design Decisions for R-Type¶

Consider all 10 R-Type instructions shown in Table 1, which is a reformatting of the rightmost columns of the equivalent table on the RISC-V green card.

Analyze this table. What do you notice? What do you wonder? The below discussion questions practice the following:

1. Read and interpret instruction fields

2. Develop your design intuition for architecture.