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This “green card” is longer than one page, due to the accessible web format. We compensate by supplementing these lookup tables with references to the official ISA and/or assembly manuals where appropriate. For a two-sided reference card with the same information, check out the PDF reference card on our course website.

Reference: The official RISC-V unprivileged ISA specification, RV32I Base Integer Instruction Set, Version 2.1. In practice, the ASM Manual will have everything you need.

1RV32I Base Integer Instruction Set

1.1Arithmetic

Table 1:RV32I Instructions: Arithmetic

InstructionNameDescriptionTypeOpcodeFunct3Funct7
add rd rs1 rs2ADDR[rd] = R[rs1] + R[rs2]R011 0011000000 0000
sub rd rs1 rs2SUBtractR[rd] = R[rs1] - R[rs2]R011 0011000010 0000
and rd rs1 rs2bitwise ANDR[rd] = R[rs1] & R[rs2]R011 0011111000 0000
or rd rs1 rs2bitwise ORR[rd] = R[rs1] | R[rs2]R011 0011110000 0000
xor rd rs1 rs2bitwise XORR[rd] = R[rs1] ^ R[rs2]R011 0011100000 0000
sll rd rs1 rs2Shift Left LogicalR[rd] = R[rs1] << R[rs2]R011 0011001000 0000
srl rd rs1 rs2Shift Right LogicalR[rd] = R[rs1] >> R[rs2] (Zero-extend)R011 0011101000 0000
sra rd rs1 rs2Shift Right ArithmeticR[rd] = R[rs1] >> R[rs2] (Sign-extend)R011 0011101010 0000
slt rd rs1 rs2Set Less Thanif (R[rs1] < R[rs2])
{ R[rd] = 1 } else {
R[rd] = 0 }		R011 0011010000 0000
sltu rd rs1 rs2Set Less Than (Unsigned)if (R[rs1] < R[rs2])
{ R[rd] = 1 } else {
R[rd] = 0 }		R011 0011011000 0000
addi rd rs1 immADD ImmediateR[rd] = R[rs1] + immI001 0011000-
andi rd rs1 immbitwise AND ImmediateR[rd] = R[rs1] & immI001 0011111-
ori rd rs1 immbitwise OR ImmediateR[rd] = R[rs1] | immI001 0011110-
xori rd rs1 immbitwise XOR ImmediateR[rd] = R[rs1] ^ immI001 0011100-
slli rd rs1 immShift Left Logical ImmediateR[rd] = R[rs1] << immI*001 0011001000 0000
srli rd rs1 immShift Right Logical ImmediateR[rd] = R[rs1] >> imm (Zero-extend)I*001 0011101000 0000
srai rd rs1 immShift Right Arithmetic ImmediateR[rd] = R[rs1] >> imm (Sign-extend)I*001 0011101010 0000
slti rd rs1 immSet Less Than Immediate (signed)if (R[rs1] < imm)
{ R[rd] = 1 } else {
R[rd] = 0 }		I001 0011010-
sltiu rd rs1, immSet Less Than Immediate (Unsigned)if (R[rs1] < imm)
{ R[rd] = 1 } else {
R[rd] = 0 }		I001 0011011-

1.2Memory

Table 2:RV32I Instructions: Memory

InstructionNameDescriptionTypeOpcodeFunct3
lb rd imm(rs1)Load ByteR[rd] = M[R[rs1] + imm][7:0] (Sign-extend)I000 0011000
lbu rd imm(rs1)Load Byte (Unsigned)R[rd] = M[R[rs1] + imm][7:0] (Zero-extend)I000 0011100
lh rd imm(rs1)Load Half-wordR[rd] = M[R[rs1] + imm][15:0] (Sign-extend)I000 0011001
lhu rd imm(rs1)Load Half-word (Unsigned)R[rd] = M[R[rs1] + imm][15:0] (Zero-extend)I000 0011101
lw rd imm(rs1)Load WordR[rd] = M[R[rs1] + imm][31:0]I000 0011010
sb rs2 imm(rs1)Store ByteM[R[rs1] + imm][7:0] =
R[rs2][7:0]		S010 0011000
sh rs2 imm(rs1)Store Half-wordM[R[rs1] + imm][15:0] =
R[rs2][15:0]		S010 0011001
sw rs2 imm(rs1)Store WordM[R[rs1] + imm][31:0] =
R[rs2][31:0]		S010 0011010

1.3Control

Table 3:RV32I Instructions: Control

InstructionNameDescriptionTypeOpcodeFunct3Funct7
beq rs1 rs2 labelBranch if EQualif (R[rs1] == R[rs2]) PC = PC + offsetB110 0011000
bne rs1 rs2 labelBranch if Not Equalif (R[rs1] != R[rs2]) PC = PC + offsetB110 0011001
blt rs1 rs2 labelBranch if Less Than (signed)if (R[rs1] < R[rs2]) PC = PC + offsetB110 0011100
bltu rs1 rs2 labelBranch if Less Than (Unsigned)if (R[rs1] < R[rs2]) PC = PC + offsetB110 0011110
bge rs1 rs2 labelBranch if Greater or Equal (signed)if (R[rs1] >= R[rs2]) PC = PC + offsetB110 0011101
bgeu rs1 rs2 labelBranch if Greater or Equal (Unsigned)if (R[rs1] >= R[rs2]) PC = PC + offsetB110 0011111
jal rd labelJump And LinkR[rd] = PC + 4;
PC = PC + offset		J110 1111
jalr rd rs1 immJump And Link RegisterR[rd] = PC + 4;
PC = R[rs1] + imm		I110 0111000

1.4Other

Table 4:RV32I Instructions: Other

InstructionNameDescriptionTypeOpcodeFunct3
auipc rd immuAdd Upper Imm to PCimm = immu << 12
R[rd] = PC + imm		U001 0111
lui rd immuLoad Upper Immediateimm = immu << 12
R[rd] = imm		U011 0111
ebreakEnvironment BREAKAsks the debugger to do something (imm = 0)I111 0011000
ecallEnvironment CALLAsks the OS to do something (imm = 1)I111 0011000

Table 5:RV32I Extension Instructions

InstructionNameDescription
mul rd rs1 rs2Multiply (part of mul ISA extension)R[rd] = (R[rs1]) * (R[rs2])

2Pseudoinstructions

See the ASM Manual and this 2024 GitHub issue discussion.

Table 6:RV32I Common Pseudoinstructions

PseudoinstructionNameDescriptionTranslation
beqz rs1 labelBranch if EQuals Zeroif (R[rs1] == 0)
PC = PC + offset		beq rs1 x0 label
bnez rs1 labelBranch if Not Equals Zeroif (R[rs1] != 0)
PC = PC + offset		bne rs1 x0 label
j labelJumpPC = PC + offsetjal x0 label
jal labelJump and LinkR[ra] = PC + 4
PC = PC + offset		jal ra label
jr rs1Jump RegisterPC = R[rs1]jalr x0 rs1 0
la rd labelLoad absolute AddressR[rd] = &labelauipc, addi
li rd immLoad ImmediateR[rd] = immlui (if needed), addi
mv rd rs1MoVeR[rd] = R[rs1]addi rd rs1 0
neg rd rs1NEGateR[rd] = -(R[rs1])sub rd x0 rs1
nopNo OPerationdo nothingaddi x0 x0 0
not rd rs1bitwise NOTR[rd] = ~(R[rs1])xori rd rs1 -1
retRETurnPC = R[ra]jalr x0 ra 0

3Register Convention

See the table from the ASM Manual, which we find the most useful. Other references include the RISC-V ELF psABI Specification (RISC-V Calling Conventions), which supercedes Volume I, V2.1, 2014: Chapter 18 Calling Convention.

Table 7:RV32I Register Convention

Register(s)NameDescriptionSaver
x0zeroConstant 0-
x1raReturn AddressCaller
x2spStack Pointer
x3gpGlobal Pointer
x4tpThread Pointer
x5-7t0-2Temporary RegistersCaller
x8s0 / fpSaved Register 0 / Frame Pointer
x9s1Saved Register
x10-11a0-1Function Arguments / Return ValuesCaller
x12-17a2-7Function ArgumentsCaller
x18-x27s2-11Saved RegistersCallee
x28-31t3-6TemporariesCaller

4Instruction Types

Table 8:RV32I Instruction Types

Type
3125
2420
1915
1412
117
60
Rfunct7rs2rs1funct3rdopcode
Iimm[11:0]rs1funct3rdopcode
I*funct7imm[4:0]rs1funct3rdopcode
Simm[11:5]rs2rs1funct3imm[4:0]opcode
Bimm[12|10:5]rs2rs1funct3imm[4:1|11]opcode
Uimm[31:12]rdopcode
Jimm[20|10:1|11|19:12]rdopcode
L10 RISC-V Data Transfer
IEC and Base-10 Prefixes
L10 RISC-V Data Transfer
References