1Learning Outcomes¶
Coming soon! We provide the animations for now.
🎥 Lecture Video
2Tracing the addi Datapath¶
Data inst[24:20] still feeds into Reg[], which still outputs R[rs2].
However, control Bsel=1 means R[rs2] data line is ignored.
3Immediate Generator Block¶
Figure 1:Immediate Generator Block
3.1I-Type¶
Figure 2:Immediate Generator Block: I-Type
3.2Multiple instruction formats (e.g., I-Type, S-Type)¶
Coming soon. We recommend revisiting this section after you have traced through stores in our datapath.
3.3Course Project Details¶
Table 1:Signals for Immediate Generator. Course project signal names, if different, are in parentheses.
| Name | Direction | Bit Width | Description |
|---|---|---|---|
| Input | inst (Instruction) | 32 | The instruction being executed |
| Input | ImmSel | 3 | Value determining how to reconstruct the immediate |
| Output | imm (Immediate) | 32 | Value of the immediate in the instruction |
Recall that the bits of the immediate are stored in different bits of the instruction, depending on the type of the instruction. The ImmSel signal, which is implemented in the control logic, will determine which type of immediate this subcircuit should generate.
The immediate storage formats are listed below:
Table 2:Immediate Storage Formats from the RISC-V Green Card.
| Type | ImmSel (default) | Bits 31-20 | Bits 19-12 | Bit 11 | Bits 10-5 | Bits 4-1 | Bit 0 |
|---|---|---|---|---|---|---|---|
| I | 0b000 | inst[31:20] | inst[30:20] | ||||
| S | 0b001 | inst[31] | inst[30:25] | inst[11:7] | |||
| B | 0b010 | inst[31] | inst[7] | inst[30:25] | inst[11:8] | 0 | |
| U | 0b011 | inst[31:12] | 0 | ||||
| J | 0b100 | inst[31] | inst[19:12] | inst[20] | inst[30:21] | 0 | |
Observations/reminders:
You should treat I*-type immediates as I-type immediates, since the ALU should only use the lowest 5 bits of the B input when computing shifts.
Recall that all immediates are 32 bits and sign-extended. (Sign extension is shown in Table 2 as inst[31] repeated in the upper bits.)