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1Learning Outcomes

🎥 Lecture Video

As mentioned in the previous section, a CPU has two types of elements, reflecting the design of many digital logic systems.

In this section, we discuss the state elements needed in a RISC-V processor. We will discuss and introduce the combinational logic blocks as we build out the full datapath.

1.1Program Counter

The Program Counter is a 32-bit register in Figure 1 and holds the value of the current instruction, i.e., instruction to execute in the current clock cycle.

"TODO"

Figure 1:The Program Counter, PC, is a single 32-bit register in the CPU.

PC Signals

Input:

  • Data: N-bit data input bus

  • Control: Write Enable bit. 1: asserted/high, 0: deasserted/low.

  • Clock signal.

Output:

  • Data: N-bit data output bus

Behavior:

1.2Register File (Regfile)

The Register File (regfile, or Reg[]) has 32 registers: register numbers x0 to x31.

"TODO"

Figure 2:The RegFile is symbolically written as Reg[] and is composed of registers x0 to x31.

Table 1:Regfile signals. Course project signal names, if different, are in parentheses.

NameDirectionBit WidthDescription
rs1 (ReadIndex1)Input5Determines which register’s value is sent to the rdata1 (ReadData1) output
rs2 (ReadIndex2)Input5Determines which register’s value is sent to the rdata2 (ReadData2) output
rd (WriteIndex)Input5The register to write to on the next rising edge of the clock (if RegWEn is 1)
wdata (WriteData)Input32The data to write into rd on the next rising edge of the clock (if RegWEn is 1)
RegWEnInput1Determines whether data is written to the register file on the next rising edge of the clock
clkInput1Clock input
rdata1 (ReadData1)Output32The value of the register identified by rs1 (ReadIndex1)
rdata2 (ReadData2)Output32The value of the register identified by rs2(ReadIndex2)

Behavior:

1.3DMEM: Data Memory

For this class, memory is “magic.” Assume a 32-bit byte-addressed memory space, and memory access occurs with 32-bit words. We go into more detail with our course projects.

For our single-cycle datapath, we must access memory twice: once during IF (Instruction Fetch) to read the instruction from memory, and once during MEM (Memory Access) if we load/store data from/to memory. We therefore need two memory blocks: IMEM and DMEM for instruction memory and data memory, respectively.[1]

The Data Memory block DMEM has edge-triggered writes, just like Reg[].

"TODO"

Figure 3:The Data Memory block DMEM. Read operations behave like combinational logic, whereas write operations occur on the rising clock edge.

Table 2:DMEM signals. Course project signal names, if different, are in parentheses.

NameDirectionBit WidthDescription
addr (MemAddress)Input32The address in memory to read from or write to
wdata (MemWriteData)Input32Data to write to memory
MemRW (MemWriteMask)Input4The write enable mask for writing data to memory
clkInput1Clock input
rdata (MemReadData)Output32Data at addr (MemAddress) from memory

Behavior: DMEM read/writes behave similarly to Regfile, though now we provide memory addresses as input, not register numbers.

1.4IMEM: Instruction Memory

The Instruction Memory block IMEM is a read-only memory that fetches instructions.[2]

"TODO"

Figure 4:In our CPU, the Instruction Memory block IMEM is read-only and behaves like combinational logic.

Table 2:IMEM signals. Course project signal names, if different, are in parentheses.

NameDirectionBit WidthDescription
addr (N/A)Input32The address in memory to read from
inst (Instruction)Output32The instruction at memory address addr(ProgramCounter)

Behavior:

Footnotes

  1. Under the hood, IMEM and DMEM are placeholders for L1 caches: L1i, L1d.

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  2. We will need to write the instruction memory when we load the program, which we ignore for simplicity.

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L20 Single-Cycle CPU Datapath I
Introduction
L20 Single-Cycle CPU Datapath I
R-Type Datapath, ALU