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1Learning Outcomes

Recall that I-Type arithmetic instructions encode an sign extension 12-bit immediate as a two’s complement integer, which is then sign-extended to a 32-bit value. While constants are frequently short and fit into the 12-bit I-Type fields, we inevitably need to encode wide immediates to build numberic constants larger than the I-type’s 12-bit imm.

RISC-V achieves wide immediates as follows:

There are two U-Type instructions: lui and auipc. These are located in the “Other” section of the RISC-V green card.

2Load Upper Immediate (lui)

From the P&H textbook (Chapter 2.10), one such instruction, lui, is Load Upper Immediate:

...load a 20-bit constant into bits 12 through 31 of a register. The rightmost 12 bits are filled with zeros.

In Table 1, we call this upper immediate immu and the 32-bit immediate imm.

Table 1:The lui instruction.

InstructionNameDescription
lui rd immuLoad Upper Immediateimm = immu << 12
R[rd] = imm

As shown in Figure 1, imm = immu << 12; this 32-bit numeric constant imm is then written to register rd.

"TODO"

Figure 1:For U-Type instructions, immu is the top 20 bits of a 32-bit-wide numeric constant imm imm.

2.1Load Immediate Pseudoinstruction

With this new instruction, we can now return to translating the li pseudoinstruction, Load Immediate. When we introduced load immediate, you may have noticed a footnote in Table 3:

This description is incomplete given the range of imm in addi. See the green-card and a later section for the full translation of load immediates.

In other words, when li must use a numeric constant wider than the 12 bits accommodated by the I-Type addi’s imm field it translates to two instructions: lui and addi.

PseudoinstructionNameDescriptionTranslation
li rd immLoad ImmediateR[rd] = immlui (if needed), addi

In other words, li translates to addi when the immediate is between -2048 and 2047. For anything larger, li translates to two instructions: lui and addi.

In general, the compiler or assembler will break large constants across the lui and addi instructions, as needed. After all, there are some important caveats to this process. Hover over the two footnotes below before continuing.

3Add Upper Immediate to PC

Coming soon. Used for J-Type instructions.

Table 2:The auipc instruction.

InstructionNameDescription
auipc rd immuAdd Upper Imm to PCimm = immu << 12
R[rd] = PC + imm

4U-Type: Fields

In order to translate lui and auipc to machine code, we need an instruction format that supports 20-bit immediates. The U-Type instruction format is only used by lui and auipc and is the one of the last rows of the instruction format table of the RISC-V green card.

"TODO"

Figure 3:The U-Type Instruction Format.

U-Type has only three fields (Figure 3):

Table 3:RV32I Instructions: U-Type

Instructionimm[31:12] (“immu”)rdopcode
auipcimm[31:12]rd0010111
luiimm[31:12]rd0110111
Footnotes
  1. And zero out lower 12 bits

  2. “Set” as in, add a sign-extended 12-bit immediate

  3. Wikipedia: Straw Man

  4. For some definition of “cute”; here, “cool math”