Summary

1And in Conclusion $\dots$ ¶

🎥 Lecture Video

1.1Instruction Translation¶

Recall that every instruction in RISC-V can be represented as a 32-bit binary value, which encodes the type of instruction, as well as any registers/immediates included in the instruction. To convert a RISC-V instruction to binary, and vice-versa, you can use the steps below. The 61C reference sheet will be very useful for conversions!

RISC-V ⇒ Binary

Identify the instruction type (R, I, I*, S, B, U, or J)
Find the corresponding instruction format
Convert the registers and immediate value, if applicable, into binary
Arrange the binary bits according to the instruction format, including the opcode bits (and possibly funct3/funct7 bits)

Binary ⇒ RISC-V

Identify the instruction using the opcode (and possibly funct3/funct7) bits
Divide the binary representation into sections based on the instruction format
Translate the registers + immediate value
Put the final instruction together based on instruction type/format

Below is an example of a series of RISC-V instructions with their corresponding binary translations.

`example.S`	`example.bin`
`main:` `addi sp,sp,-4` `sw ra,0(sp)` `addi s0,sp,4` `mv a0,a5` `call printf` `...`	`...` `11111111110000010000000100010011` `00000000000100010010000000100011` `00000000010000010000010000010011` `00000000000000000000010100010011` `00000000010001000000000011101111` `...`

2Textbook Readings¶

P&H 2.5, 2.10

3Exercises¶

Check your knowledge!

3.1Conceptual Review¶

Solution to Exercise 1 #

True. The opcode field of an instruction uniquely identifies the instruction type and allows us to identify the instruction format we’re working with. The opcode is located in the lowest 7 bits of the machine instruction (bits 0-6).

Solution to Exercise 2 #

False. This is a bit of a trick question. It is true that every regular instruction in RISC-V will always be encoded in 32-bits. However, li is actually a pseudo-instruction! Recall that pseudo-instructionscan translate into one or more RISC-V instructions. In this case, li will be translated into an addi and lui instruction. Therefore, li x5 0x44331416 will actually be encoded in 64-bits, as it represents two RISC-V instructions.

Solution to Exercise 3 #

False. Branch instruction offsets have an implicit zero as the least significant bit, so we can only move the PC in offsets divisible by 2 (refer back to this section for an explanation why this is!). The full offset for a branch instruction will be the 13-bit offset {imm[12:1], 0}, where we take the immediate bits from our instruction’s binary encoding and add the implicit zero.

3.2Short Exercises¶

Solution to Exercise 4 #

Note that since we have 32 different registers in RISC-V, we need 5 bits to encode them. Looking at the 61C reference sheet, we can see that s0 refers to the x8 register. To get the final answer, we convert 8 into binary: 0b01000. Following the same procedure as above, we get the rest of the answers...

s0: x9 = 0b01000
sp: x2 = 0b00010
x9: x9 = 0b01001
t4: x29 = 0b11101