The RISC-V 5-Stage Pipeline - CS 61C Course Notes

1Learning Outcomes¶

Explain how pipeline registers pass data in-between stages of the 5-stage pipeline.
Contrast the ways that the five-steps of a RISC-V instruction are implemented in a 5-stage pipelined processor and a single-cycle processor.
Discuss approaches to pipelining control.

🎥 Lecture Video

In this section, we transform the single-cycle processor into our RISC-V five-stage pipelined processor. A pipelined processor “separates” the five steps to a RISC-V instruction into stages, where instructions execute in stages, and stages of different instructions execute in parallel during the same clock cycle.

2Pipelined Datapath¶

Toggle between the visualizations below to visualize the five-stage pipelined datapath. At each rising clock edge, pipeline registers carry data and control signals to the next stage. We discuss control below.

5-Stage Pipelined Datapath

Single-Cycle Datapath

"TODO" — Figure 1:Five-stage RISC-V datapath diagram. Pipeline registers are inserted between stages to hold signals until the next clock cycle.

Just like the single-cycle datapath, in the five-stage pipeline, data and control signals still generally move left to right. There are also still two loops. We extend our original quote from P&H 4.7:

Instructions and data move generally from left to right through the five stages as they complete execution. Returning to our laundry analogy, clothes get cleaner, drier, and more organized as they move through the line, and they never move backward.
There are, however, two exceptions to this left-to-right flow of instructions:
The write-back stage, which places the results back into the register file in the middle of the datapath
The selection of the next value of the PC, choosing between the incremental PC and the branch address from the MEM stage
Data flowing from right to left do not affect the current instruction; these reverse data movements influence only later instructions in the pipeline. Note that the first right-to-left flow of data can lead to data hazards and the second leads to control hazards.^[1]

We define pipeline registers by the two stages they are inserted between, e.g., IF/ID pipeline registers refer to the registers between the IF and ID stages. From P&H 4.7:

Returning to our laundry analogy, we might have a basket between each pair of stages to hold the clothes for the next step.

3Five Stages of the RISC-V Pipelined Processor¶

We now revisit the five steps to a RISC-V instruction in the context of our new five-stage pipelined datapath in Figure 1. Here are the five steps.

And here are the stages of the five-stage RISC-V pipelined processor, one step per stage.

Five stages of a RISC-V instruction

Instruction Fetch (IF): Fetch the current instruction from IMEM and compute PC + 4.
An instruction concurrently executing in a later stage (MEM) sets the control signal PCSel to determine the next instruction to execute.
Instruction Decode (ID): Decode the operation from the bits of the instruction, read registers from the RegFile, and generate a 32-bit immediate.
The IF/ID pipeline registers provide the instruction bits.
Execute (EX): Use the ALU to either perform register-register arithmetic (R-Type), register-immediate arithmetic (I-Type, S-Type), PC-immediate arithmetic (loads, B-Type, jal, auipc), or get the immediate (lui).
The ID/EX pipeline registers provide the operands for the ALU, as well as the instruction bits that determine the ALU operation.
Additionally, use the Branch Comparator to compare the source register values, and pass the results into the control unit.
Memory Access (MEM): Load data from (or store data to) DMEM.
The EX/MEM pipeline registers provide the memory address and the data to write.
Additionally, the results of the Branch Comparator are known at this time. Use the control unit to determine the PCSel control signal. In a later section, we discuss how this design may lead to control hazards, or potential out-of-order execution of instructions.
Write Back (WB): Write back to the RegFile.
The MEM/WB pipeline registers provide the data to write, as well as the instruction bits that determine what to write (for the WBSel mux).
Recall that in our discussion of instruction timing the WB phase of the single-cycle datapath simply included a MUX and register setup time, because it was assumed that the RegFile element performed rising-edge triggered writes. In a later section, we discuss a modified RegFile element that can perform writes on the falling edge of the clock.

4Pipeline Registers in the 5-Stage Datapath¶

Below, we explain Figure 3 from the perspective of what is fed into each set of pipeline registers. For example, when discussing IF/ID registers, we describe the instruction currently executing in the IF stage.

Figure 3:Animation that steps through the enumerated text in this section. Access original Google Slides. A more complete picture is in Figure 6.

IF/ID: Show Explanation

An instruction that is currently in the IF stage passes the following into IF/ID pipeline registers:

PC: The PC (i.e., address of this instruction) is saved in case it is needed in a later clock cycle, e.g., in the EX stage, where conditional branch/unconditional jump instructions use the ALU to compute PC-relative addresses.
inst: The instruction data, which is read from IMEM during this stage, is saved for immediate use in the instruction’s next stage, ID, e.g., to determine source registers. Recall that in the IF stage, the computer cannot know which type of instruction is potentially being fetched, so it must prepare for any instruction, passing potentially needed information down the pipeline (P&H 4.7).

ID/EX: Show Explanation

An instruction that is currently in the ID stage passes the following into ID/EX pipeline registers:

PC: Unchanged but may still be needed by this instruction in a later stage (see IF/ID discussion). We pass this data directly between the IF/ID and ID/EX pipeline registers.
RegReadData1: The rdata1 output signal from RegFile read during this instruction’s ID stage.
RegReadData2: The rdata2 output signal from RegFile, read during this instruction’s ID stage.
imm: The output of the immediate generator, produced in this instruction’s ID stage.
inst: Again, we pass the instruction along with its data onto the instruction’s next stage, EX.

EX/MEM: Show Explanation

An instruction that is currently in the EX stage passes the following into EX/MEM pipeline registers:

PC: Unchanged as part of this instruction’s EX stage but may be needed in later cycles of this instruction, e.g., with auipc.
ALUOut: The ALU result, computed during this stage.
RegRead2: The data in register rs2; if this instruction is a store (S-Type), it will need this data in its MEM stage.
inst: Again, we pass the instruction along with its data onto the instruction’s next stage, MEM.

MEM/WB: Show Explanation

An instruction that is currently in the MEM stage passes the following into MEM/WB registers.

ALU: Unchanged in this instruction’s MEM stage, but needed as one of the options to write back to the RegFile in this instruction’s next stage, WB.
PC+4: To avoid sending both PC and PC + 4 down the pipeline, we add an additional subcircuit to recalculate PC + 4 as one of the write-back options in this instruction’s next stage, WB.
Mem: The result of reading DMEM, read in this stage.
inst: We are repeating ourselves here. :-)

5Pipelined Control¶

Since pipelining the datapath leaves the meaning of the control lines unchanged, we can use the same control values but now group together the control signals by pipeline stage, as in Table 1 and Figure 4.

Table 1:Signals for control logic, grouped by pipeline stage.

Name	Stage
`ImmSel`	`ID`
`BrUn`	`EX`
`ASel`	`EX`
`BSel`	`EX`
`ALUSel`	`EX`
`MemRW`	`MEM`
`PCSel`	`MEM`
`WBSel`	`EX`
`RegWEn`	`WB`

We note there is nothing special to control in the IF stage, because the control signals to read instruction memory and to write the PC are always implicitly asserted. PCSel, the control signal to determine what to write to the PC, is determined in MEM.

5.1Implementing Pipelined Control¶

Implementing control means setting these control lines to the correct values in each stage for each instruction. We discuss two approaches below.

One approach computes as many control signals as possible during instruction decode (ID) because all control signals but PCSel can be derived from the instruction. As shown in Figure 5, this extends the pipeline registers to include control information to pipeline control “words” between stages. This approach reuses much of the control circuitry from our single-cycle processor.

Figure 4 shows a second approach. Each stage now has a separate control unit that determines the control signals based on the instruction currently executing in that stage. This is illustrated in Figure 4 by the inputs to the different control signal groups: inst (ID), inst (EX), inst (M), and inst (WB).

6Summary¶

The full five-stage pipeline processor is shown in Figure 6; this is also on the course reference card.

The 5-stage pipeline we have studied is commonplace in many devices: cars, appliances, etc.

Footnotes¶

We discuss hazards in a later section of this chapter.
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