Skip to article frontmatterSkip to article content
Site not loading correctly?

This may be due to an incorrect BASE_URL configuration. See the MyST Documentation for reference.

1Learning Outcomes

🎥 Lecture Video

2Visuals

"TODO"

Figure 1:Superscalar processors start multiple instructions per clock cycle.

Superscalar processors start multiple instructions per clock cycle. In our Iron Law of Processor Performance, superscalar processors have CPI > 1.

"TODO"

Figure 2:ARM A53 Benchmark (horizontal yellow line where CPI=1\text{CPI}=1).

L25 Pipelining II: Hazards
Control Hazards
L25 Pipelining II: Hazards
Summary