1And in Conclusion¶
🎥 Lecture Video
The critical path changed based on instruction. Not all instructions use all hardware units, and therefore not all instructions are active in all five phases of execution (“stages” is the terminology we use for pipelined processors).
The controller pecifies how to execute instructions and it is implemented as ROM (read-only-memory) or as logic gates.
2Textbook Readings¶
P&H 4.4, 4.5
3Exercises¶
Check your knowledge!
3.1Short Exercises¶
True/False: The single cycle datapath uses the outputs of all hardware units for each instruction.
Solution
False All units are active in each cycle, but their output may be ignored (gated) by control signals
True/False: It is possible to execute the stages of the single cycle datapath in parallel to speed up execution of a single instruction.
Solution
False Each stage depends on the value produced by the stage before it (e.g., instruction decode depends on the instruction fetched).
True/False: Stores and loads are the only instructions that require input/output from DMEM.
Solution
True For all other instructions, we don’t need to read the data that is read out from DMEM, and thus don’t need to wait for the output of the MEM stage.